A multi-core system is an electronic system comprising a plurality of computation units called cores. The multi-core processors are an example thereof. Such a processor thus includes a plurality of cores in one and the same electronic chip and can comprise some tens to some hundreds of cores.
A multi-core system makes it possible to perform a number of processing operations in parallel. It is then possible to achieve computation powers greater than that of a single-core system while limiting the heat dissipation phenomenon. However, such systems have to include means for intelligently managing the resources shared by these cores, such as, for example, means for managing access to the cache memory of each core and to the memory external to the cores, the external memory also being called central memory or main memory. As a reminder, the cache memory is a type of memory usually placed in proximity to the hardware resource that uses it and whose objective is to store data copies so as to allow rapid access to this data item by said resource. To manage the cache memory, methods for maintaining the consistency of the data stored in this memory are usually used.
One method for maintaining cache memory consistency notably allows for the management of multiple copies of one and the same digital data item, said copies being situated in the cache memories associated with different cores. Maintaining the consistency of the data copies notably makes it possible to simplify the programming of the multi-core systems.
When a cache fault is detected, that is to say a data item sought by a core is not available in cache memory, said computation core has to search for the data item externally, that is to say either in the cache memory of another core, or in the main memory. For this, a core usually uses a memory interface implementing a memory interface protocol in order to access the data stored outside said core. The result of the execution of the memory interface protocol is the sending of messages via, for example, a communication bus that enable the cores to communicate with one another and with the main memory. These different operations induce, for a core, the consumption of computation resources to execute operations associated with the memory interface protocol. Furthermore, the set of messages sent can occupy a significant portion of the bandwidth of the communication bus and this can be prejudicial to an efficient operation of the multi-core system. In practice, if the communication bus is congested, the application running on the multi-core system is slowed down. A purpose of the method for maintaining memory consistency is notably to reduce the execution time associated with the memory interface protocol and to limit as far as possible the number of messages sent.